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ISL8200M
OC trip set by 1.2V comparator can be lower than
108μA trip point as shown in Equation 6.
In a high input voltage, high output voltage
application, such as 20V input to 5V output, the
? I OC + ---------------- ? ? ? ---------------- – T MIN_OFF ? ? ? ? RDS
? ?
2F SW
R ISEN1 = -----------------------------------------------------------------------------------------------------------------------
? V OUT 1 – D ?
L
I TRIP
(EQ. 6)
inductor ripple becomes excessive due to the fix
internal inductor value. In such application, the output
current will be limited from the rating to approximately
70% of the module’s rated current.
R ISHARE = ---------------
1.2V
I TRIP
R ISET = R ISHARE ? N CNTL
When OCP is triggered, the controller pulls EN low
immediately to turn off UGATE and LGATE.
R SEN-EX × R SEN-IN
R SEN = --------------------------------------------------------
where N CNTL is the number of the ISL8200M modules
in parallel or multi-module operations; I TRIP = 108μA;
I OC is the load overcurrent trip point; T MIN_OFF is the
minimum U GATE turn off time that is 350ns; R ISHARE
in Equation 7 represents the total equivalent resistance
in ISHARE pin bus of all ICs in multiphase or module
parallel operation.
ISL8200M has a low-side FET with typical r DS(ON) of
9m Ω (V GS = 10V, I DS = 30A).
Note: ISL8200M has integrated 2.2k Ω resistance
(R SEN-IN ). Therefore, the equivalent resistance of R SEN
is:
(EQ. 7)
R SEN-EX + R SEN-IN
The OC trip point varies in a system mainly due to the
MOSFET r DS(ON) variations (over process, current and
temperature). To avoid overcurrent tripping in the normal
operating load range, find the R SEN resistor from
Equation 8 of I PEAK with:
1. The maximum r DS(ON) at the highest junction
temperature
2. The minimum I SOURCE from the “Electrical
Specifications” table on page 9.
For overload and hard short condition, the overcurrent
protection reduces the regulator RMS output current
much less than full load by putting the controller into
hiccup mode. A delay time, equal to 3 soft-start
intervals, is entered to allow the disturbance to be
cleared out. After the delay time, the controller then
initiates a soft-start interval. If the output voltage
comes up and returns to the regulation, PGOOD
transitions high. If the OC trip is exceeded during the
soft-start interval, the controller pulls EN low again.
The PGOOD signal will remain low and the soft-start
interval will be allowed to expire. Another soft-start
interval will be initiated after the delay interval. If an
overcurrent trip occurs again, this same cycle repeats
until the fault is removed.
Oscillator
The Oscillator is a sawtooth waveform, providing for
leading edge modulation with 350ns minimum dead
time. The oscillator (Sawtooth) waveform has a DC
offset of 1.0V. Each channel’s peak-to-peak of the
ramp amplitude is set to proportional the voltage
applied to its corresponding FF pin.
Frequency Synchronization and Phase Lock
Loop
The FSYNC_IN pin has two primary capabilities: fixed
I OC > I OUT ( MAX ) + -------------
3. Determine I OC for:
( Δ I L )
2
(EQ. 8)
frequency operation and synchronized frequency
operation. By tying a resistor (R FS ) to PGND1 from the
FSYNC_IN pin, the switching frequency can be set at
any frequency between 700kHz and 1.5MHz. ISL8200M
where Δ I L is the output inductor ripple current.
The relationships between the external R SEN-EX values
and the typical output current I OUT(MAX) OCP levels for
ISL8200M are as follows:
TABLE 2.
has integrated 59k Ω resistor between FSYNC_IN and
PGND1, which set the default frequency to 700kHz.
T he frequency setting curve shown in Figure 27 is
provided to assist in selecting the an externally
connected resistor RFS-ext between FSYNC_IN and
PGND1 to increase the switching frequency.
R SEN-EX
( Ω )
OPEN
50k Ω
20k Ω
10k Ω
5k Ω
3k Ω
2k Ω
17
OCP (A) @
V IN = 12V
17
15.5
14.5
14
12.5
11
8
FN6727.1
February 26, 2010
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